National Semiconductor Corp may have been roundly bested in the microprocessor CPU market with its NS32000 family – the part is primarily used these days only in special versions optimised for graphic and laser printer control – but it is not ready to exit the general purpose microprocessor market without a fight. At next month’s International Solid State Circuits Conference in San Francisco, the Santa Clara company plans to announce its entry into the RISC business by describing a superscalar 64-bit part that will take advantage of the intrinsic simplicity of RISC by packing two integer units, a single and double precision floating point unit and signal processing circuitry, plus separate instruction and data caches to deliver 100 MIPS with a clock speed of 50MHz. According to the pre-conference come-on seen by Electronic News, the bus and clock designs will also support conventional system design at 25MHz while operating internally at 50MHz. The part presumably uses the old minicomputer technique adopted by IBM in its top-end Summit models of the ES/9000 of automatically splitting the instruction and data stream into two and passing half through each integer unit (CI No 1,506) to achieve the claimed 100 MIPS performance. Although the RISC market is already regarded as overcrowded, there is a widespread view, especially in Japan, that 64 bits will be required for all the things that people are going to want to do at the desktop over the next few years, and given that the same company or companies seldom dominate two successive generations of microprocessor, there is still all to play for in the first 64-bit generation, in which Japan’s G-Micro Tron chips may also contend.
