National Semiconductor Corp, Santa Clara, California has announced the first of a family of programmable logic devices that are claimed to provide high density without sacrificing speed or raising power consumption: the Multiple Array Programmable Logic family uses a proprietary architecture in a patented paged configuration; the densities range from the 28-pin devices to planned 68 pins, representing densities of 1,000 to 4,000 gates; worst-case system speed of 45MHz is guaranteed across the family, and the first, the MAPL128, is available in a 28-pin PLCC package; a second device, the MAPL144, will be offered in a 44-pin package, and it has the same structure and size as the MAPL128, but will allow for eight additional dedicated output pins, a dedicated output enable pin, and the 44-pin Jedec standard multiple power and ground pins; the MAPL architecture allocates user-defined product and sum terms depending on logic design needs.
