Motorola Inc says it will be first to market with a new chip manufacturing technique it says will cut product testing times, saving up to 15% on current manufacturing costs and 25% on manufacturing cycle times. The technology, which enables burn- in testing of integrated circuits at the wafer level, was announced as part of a joint agreement between Motorola, semiconductor equipment manufacturer Tokyo Electron Ltd, and electronics supplier WL Gore & Associates Inc. The three have been working on the project for 18 months. Carrying out the burn- in process on semiconductors while they are still in wafer form contrasts with the current method of post-assembly burn-in, and means that more extensive testing can be completed at an earlier stage, and that lower grade wafers can be eliminated. Motorola says the technique is most suitable for complex chips such as PowerPC, fast static RAM, and the new generation of system-on-a- chip products it’s currently investing in. Gore provided technology for flat, interconnected multi-layer boards and a contact membrane between board and wafer that stands up to the 150 degree burn-in temperatures while still working at room temperatures. The technique requires extensive refitting of back-end non-wafer manufacturing plants, and with TEL’s help will be building the first of a number of new bump assembly and testing plants, BAT 1, in Austin Texas, which will include all the final manufacturing processes under one roof. Motorola expects other chip manufacturers to introduce similar technology in the near future, but says it will be first to market with the new technology when its plant becomes ready for initial production in the first quarter of 1999.
