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April 26, 1988

MOTOROLA PREVIEWS FORTHCOMING 68040 CHIP

By CBR Staff Writer

With 15m 68000 family processors installed, Motorola understandably retains its interest in the complex instruction set market, and in order to reassure customers of the continuing development of the 68000, the company has previewed details of its development stage third generation MC68040 chip, and says that it will not be the last of the 68000 line. The 68040, which will include 1m active devices, is being designed for an integer unit rating of 15 MIPS, floating point performance of 4 MFLOPS. The single chip integrates a 68030-compatible integer processing unit, IEEE compatible floating point unit, independent 8Kb instruction and data caches, and a paged memory management unit. Parallel instruction execution will be achieved by using multiple independent execution pipelines, multiple internal buses and full internal Harvard architecture, with separate physical address space caches for instruction stream and data stream access. Bus monitoring hardware will allow direct support of multiprocessing applica tions. Motorola gave no indication of when it would launch the 68040.

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