Motorola Inc says the G4 MPC7400 chip it is supplying to Apple Computer Inc (though not in enough quantities at present – see separate story) is the first of a family of new processors in the latest generation of its PowerPC family. The PowerPC roadmap has now been outlined for at least two more generations, keeping backward compatibility and using the current core instruction set and architecture, which Motorola contrasted to Intel Corp’s major break from the x86 to Merced.
The G1 PowerPC was first introduced in 1991 with the 601 chip. Originally a desktop chip, the 601 continues to be used as an integrated processor for the transportation markets and for communications and consumer markets, and the 603e core is now the basis for is for the MPC8260 and 8240 communications engine. Similarly, the G3 740, still used by Apple as a desktop chip and still with its own 7xx roadmap, will be also used as the basis for 83xx communications chips.
Beyond that, the current G4 7400, with Altivec vector processing technology, on-die cache and using Motorola’s HIP5, 0.15 micron physical gatelength copper technology won’t be the last in the G4 family, according to Motorola spokesperson Will Swearingen. The G4 is an entire generation, not just one chip. Swearingen promised several other members of the family, clock speeds of up to 1GHz and a migration to silicon-on-insulator processes. One of the new families is expected to be previewed at the Microprocessor Forum in San Jose next month by Motorola chip architect Naras Lyengar. There will also an 84xx family of communications chips. Motorola says it doesn’t expect the AltiVec technology used in the 7400 G4s to move quickly into the low-cost embedded systems space, and won’t comment on how AltiVec will be implemented in future PowerPCs.
After the G4 comes the G5. Motorola isn’t giving away any dates, but says the G5 won’t emerge until 2001 at the earliest. It will be based on a highly extensible, flexible architecture and will feature a new pipeline – the current four-stage fat pipeline used by the G4 is the same one as that used in the G3 750, and makes it harder for Motorola to move the PowerPC up to higher clock speeds. Motorola argues it’s comfortably beating Intel’s Pentium III performance even with lower clock rates. In any case, the re-achitected pipeline will enable Motorola to take the G5 up to 2GHz clock speeds and beyond. The chip will also feature a new bus topology, and will be implemented in both 64-bit and 32-bit implementations, all backwards compatible. The G5 will be the first to use Motorola’s 0.10 micron process with silicon on insulator in the initial design.
Motorola says the PowerPC roadmap is now unique to itself, and doesn’t correspond to any plans by its old partner, IBM Corp. However, the two are still working together to define Book E definitions for embedded PowerPCs, from which base both companies will produce their own implementations. The first Book E-based products aren’t likely to emerge until the G5 time frame, said Swearingen.
