Motorola Inc’s 64-bit superscalar implementation of its RISC, the 88110, was technically disclosed last week at the Microprocessor Forum in San Francisco, meaning that the company gave details on just about everything but price and availability. The revelations will be repeated in Europe next week at the 88open general meeting in Amsterdam. Combining all the functionality of the 88100 CPU and 88200 cache and memory management units onto a single chip, the plus points for the 88110 include a high degree of parallel instruction execution, and on-chip 80-bit floating point and 64-bit graphics units. A secondary cache controller, the 88410, is also available for particularly demanding applications, with cache sizes from 256Kb to 1Mb. It is implemented in 0.8 micron triple-level metal CMOS, Motorola says it can easily be shrunk to 0.65 micron technology without design modifications. It has less than 1.3m transistors. The thing was called equivalent to, if not better than, the MIPS Computer Systems Inc R4000, but without the R4000’s large external cache. A SPECmark of 63 was quoted. Graphical capabilities are said to be five times those of the Intel Corp 80860. Motorola has apparently recently produced its first functional silicon, and won’t talk about marketing issues until it has larger, sample quantities of the device available. Rumour has it the yield is pretty clean.
