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October 19, 1997updated 01 Sep 2016 6:29pm


By CBR Staff Writer

Motorola Inc is challenging Advanced RISC Machines Inc in its core marketplace with a brand new microRISC architecture aimed at portable wireless communications, computer devices and intelligent automotive systems, unveiled at the Microprocessor Forum last week. The M-Core microRISC core, a 32-bit part, has been designed for high levels of memory efficiency and low power consumption, and Motorola claims it will provide some stiff competition for the ARM Thumb, the MIPS Technology Inc tinyRISC and Siemens AG’s recently launched Tricore part (CI No 3,249). It says parts scaled down from computer CPUs, such as its own PowerPC part, aimed at higher powered embedded processing jobs, just aren’t flexible enough . M-Core is the result of a three year development project carried out for an individual Motorola customer. It is a traditional load-store RISC engine executing 16-bit instructions with 32-bit internal data path for instructions and coding, four stage pipeline and 96 instructions set optimized for code density and memory efficiency. Motorola has had silicon for over a year. Using a 0.36 micron process, current implementations operate at 1.8 volts and 50MHz, for operation on a pair of AA batteries. A near-term goal is to get it down to sub one-volt, single cell operation. Motorola’s obviously lined up an impressive level of advanced business which it won’t yet disclose, as a bevy of software tools vendors and real-time operating systems vendors have agreed to support the launch. They include Diab Data, Integrated Systems Inc, Microtec Inc, Summit Design Inc, Hewlett-Packard co and Microwave Systems Corp. Motorola will license the part to other vendors, but next year will launch its own parts, under the PowerStrike name. The first of these will sample late in the first quarter of next year, for general availability in the second quarter.

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