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November 29, 2009

MoSys launches 40nm DDR3, DDR3/2 combo PHYs

Claims to support datarates of up to 2133Mbps

By CBR Staff Writer

MoSys, a supplier of embedded memory and high-datarate parallel and serial interface IP, has launched DDR3 and DDR3/2 combo PHYs.

The company claims that its fully integrated offering complies with the new DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3/2 DRAM devices.

The DDR3/2 PHYs can achieve datarates up to 1600Mbps in a wirebond package and 2133Mbps in flip chip packaging, making them suitable for high performance and cost sensitive designs.

MoSys’ DFI 2.1 compliant DDR 3/2 PHY product is available to chip designers using 40nm and 65nm processes, and its DDR 3/2 Combo PHY device is available in both wirebond and flipchip configurations. Offering a choice of 1.8V or 2.5V IO FETs, the DDR PHYs support datarates up to 2133Mbps, the company said.

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David DeMaria, vice president of business operations at MoSys, said: “DDR3 is rapidly gaining adoption as the next generation of the DDR memory interface. The availability of our DDR3/2 Combo PHY and its seamless interoperability with Denali’s memory controller ensures speedy time-to-market for our customers’ chip designs.

David Lin, vice president of marketing at Denali Software, said: “Our high-performance memory controllers and predictable protocol verification portfolio are the industry’s most widely used, silicon-proven solutions. MoSys’ DDR3/2 Combo PHY extends our ability to provide best-in-class, end-to-end memory interconnect solutions to our mutual customers.”

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