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July 22, 2010

MoSys unveils GigaChip Alliance for serial chip-to-chip communications

To provide high-performance systems in networking, computing and storage markets

By CBR Staff Writer

MoSys, a provider of differentiated high-density memory and high-speed interface (I/O) intellectual property (IP), has unveiled the GigaChip Alliance, which provides companies with a new class of low-cost, high-speed, high-performance systems in networking, computing and storage markets.

The GigaChip Alliance, an ecosystem of semiconductor device suppliers in support of the GigaChip Interface which is a board-level, open, CEI-11 compatible interface, enables efficient serial chip-to-chip communications in next generation high-performance networking, computing and storage systems.

The company said that through the GigaChip Alliance, participating companies will collaborate on expanding the GigaChip Interface for high-speed serial chip-to-chip applications and developing industry-wide open interoperability standards and tools to accelerate the adoption of serial chip-to-chip based system designs.

A 16-lane GigaChip Interface can replace up to six separate DDR3 parallel interface busses to memory, and increase bandwidth density performance by 4 times, while reducing system power and interface costs by 2 to 3 times, which will be required to realise line cards with aggregate throughput beyond 100G, in future high end networking systems, the company said.

David DeMaria, vice president of Business Operations at MoSys, said: "Our goal is to revolutionise serial chip-to-chip communications with the GigaChip Interface. Towards that end, we are making the GigaChip Interface an open protocol and encouraging widespread use by potential partners and customers. The GigaChip Alliance will facilitate industry-wide adoption and evolution of this protocol."

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