Mosel Inc of Sunnyvale, California has a new high performance cache subsystem for 80486 SimulCache, uses a concurrent write back algorithm, and the concurrency enables the CPU to read and write to cache, while the cache performs housekeeping tasks; the SimulCache becomes a concurrent memory transaction processor, absorbing memory transactions and re-ordering them to meet the different needs of CPU and system; the MS441 controller integrates logic associated with a cache, including tag memory and comparator, and this enables the controller to support two way set associativity to 33MHz and higher; the MS443 Intelligent Dual Port Burst Memories, with 8nS access time, allow high speed burst reads and writes to the CPU and to Main Memory simultaneously; the product supports 80486 style burst reads, and adds a burst write capability that is said to result in improved throughput and reduction of overall bus activity; SimulCache consists of one MS441 Cache Controller and four MS443 Dual Port Burst Memories to create a 64Kb configuration, and it is compatible with the 80386 and 80486 CPUs up to 33MHz, and with 80386 and 80486 core logic chip sets; partitioning makes the cache subsystem independent of the input-output bus, so that it can be used with AT, EISA or Micro Channel kit; volume is set for the summer at $65 for 10,000-up, $114 for 1,000-up.
