Mitsubishi is readying a new version of its M32R/D series of hybrid processors (CI No 3,055), the M32Rx/D – dubbed eRAM by the company. The chip combines a 32-bit RISC processor with 4Mb DRAM on a single piece of silicon. The processor’s clock speed has been increased to 100MHz with a 128-bit internal bus between the CPU and the on-chip memory, according to Embedded Microprocessor Watch. The architecture of the external bus has been widened to 32-bits and it is faster than before at 25MHz. The hybrid processor concept is something that Mitsubishi has been working on since 1993 and the company released the first such chip in 1996 (CI No 2,898). The chip takes up less space than a standard CPU and DRAM set-up, has lower power consumption and is a fairly low cost component – previous M32R/Ds were around $80. However, despite the advantages of the M32R/D series for embedded applications such as personal digital assistants, the chip has not been the smash hit that Mitsubishi expected with PDA set-top box and multimedia chip manufacturers. This is partly down to the unfamiliar nature of the M32 RISC processor, a situation that will somewhat alleviated by Mitsubishi’s tie-up with Motorola Inc (CI No 3,261). This should give the M32R/D series combining Motorola’s popular 68k/ColdFire embedded processor architecture with the design advances of the eRAM technology – the chip usually completes processing operations in one cycle and reduces latency compared to board-level interconnects because of the internal bus between the CPU and the memory. The sparse Mitsubishi eRAM roadmap suggests that the first 64Mb chips using ColdFire will arrive sometime in 1999, with 256Mb chips due sometime in 2000.
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