MIPS Technologies Inc is due to reveal its T5 Terminator Alpha AXP-beater at the Microprocessor Forum this week, Unigram says. The T5, to appear as the R10000, will be the successor to MIPS’ R4000 line of general purpose RISCs and has been under development since before Silicon Graphics Inc bought MIPS. The 64-bit part is a $150m-plus development effort by MIPS’ fab partners, including LSI Logic Corp, Integrated Device Technology Inc, Toshiba Corp and Siemens AG. It was originally aiming for 200 SPECint92 and 300 SPECfp92 – performance marks which would now appear unremarkable – but the fabs have revved the specification to compete with the fastest RISCs now on the market, seeing a part that will compete with Digital Equipment Corp’s latest 21164 Alpha AXP which is tagged at 330 SPECint92 and 500 SPECfp92 – three or four times the performance of R4400. R10000 has a new bus said to perform at more than 1Gbps and has been designed – like UltraSparc, PowerPC 620 and other next-generation RISCs also expected to appear at the event – from the ground-up for multiprocessing, whether it be on the desktop or in supercomputers and honed to run Unix and Windows NT database environments. It was close to taping-out a few weeks back, and first silicon is due early next year. Boxes won’t be far behind as vendors have been designing R10000 systems using simulation.
