MIPS Technologies Inc’s superscalar, out-of-order execution T5 Terminator RISC is already being touted as an Alpha AXP-beater. Our sister publication ClieNT Server News reports that MIPS and its partners have been tweaking the T5 so it will come close to matching Alpha’s performance, though MIPS says these kinds of measurements are meaningless in terms of real applications, and that bandwidth and cacheing parameters must be considered too. The T5, which will include a new generation high-speed bus and is nearly ready, will be described at next month’s Microprocessor Forum in San Francisco. Other highlights there should include more details of Sun’s 64-bit, bi-endian UltraSparc, expected to execute up to four instructions and two MPEG-2 video decompressions at once.
