Sunnyvale, California-based MIPS Computer Systems Inc has announced a new version of its R3000 RISC microprocessor and says it solves the problem that DEC MIPSstations are incompatible with other MIPS machines because DEC changed the byte ordering: the new part enables applications to run on machines configured in either big endian or little endian byte order without the need for recompilation. MIPS says the new R3000A RISC completed certification for its five semiconductor partners, which means that users are assured that parts from any of the partners – NEC Corp, LSI Logic, Siemens AG, Integrated Device Technology and Performance Semiconductor will be pin- and specification-compatible. The R3000A enhanced version of the R3000, is claimed to be the highest performance CMOS microprocessor commercially available with system performance of 33 VAX MIPS at up to 40MHz. It draws 20% less power than the E3000, has additional features for building fault-tolerant computers, and needs fewer statics for cache.
