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July 23, 1997updated 05 Sep 2016 12:13pm

MIPS R12000 EXCEEDS EXPECTATIONS; SGI MERGES H1/H2 PROJECTS

By CBR Staff Writer

More details are now emerging of the forthcoming MIPS R12000 RISC processor, with Silicon Graphics claiming the part has exceeded all design expectations. The R12000, an implementation of the current MIPS IV RISC architecture (CI No 3,158) moves to the tape out stage in a few weeks, and according to Silicon Graphics, performs and scales so well in prototype testing that it is already pushing up into the space supposed to be occupied by H1, the first of the next-generation Mips V architecture parts. That development is accordingly being merged with that of its H2 follow-on, to create a single H1/H2 part, with another team set off to work on a further high-end processor. The R12000 is expected to go into volume production by mid-1998 as a 0.25 micron design, in speeds up to 300MHz. It includes greater out- of-order execution than the current Mips R10000, eliminates some redundancies in the cycle, and is faster internally. In its original specification the part was slated to deliver a 50% performance improvement over the current R10000 device. Along with Silicon Graphics systems, all four Cray architectures, including the current DEC Alpha and ECL vector machines, are being moved over to single Mips processor architectures, though it’s not clear which will go when.

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