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Technology / AI and automation


MIPS Computer Systems Inc has been lifting the veil on its third generation RISC processor, the R4000, a full 64-bit implementation of its architecture, and according to MIPS the first true 64-bit RISC implementation. In the view of MIPS, complex instruction set technology will essentially die at 32-bits – third generation RISCs imply multiple instruction issue processors. The R4000 uses superpipelining techniques to achieve this, and includes 64-bit virtual addresses, integer arithmetic-logic unit, and integer registers, in addition to the 64-bit paths to cache and main memory and on-chip floating point unit that often make up the sole constituents of claimed 64-bit implementations. The R4000 also includes 64-bit compatibility with 32-bit products, allowing it to take full advantage of current software technology. Its initial performance rating, expected to be around 50 MIPS, will be improved when MIPS introduces its first 64-bit compiler later this year or early next – the initial machine will come with a 32-bit compiler. Not all software will require 64-bit operation, says MIPS, which expects 32-bit and 64-bit software to be running side by side by the end of the decade. Large database applications, technical applications with display list graphics or large data sets, and next generation, highly complex applications will gain the most benefit. MIPS says that the R4000 will provide a smooth transition through the 32-bit crisis, brought on by the need for leading edge applications to burst the 4Gb address space barrier of 32-bit systems. MIPS claims the crisis will occur as early as 1991, but no later than 1994. With 8Kb on-chip data and instruction caches, the R4000 also supports secondary cacheing and hooks for multi processing. MIPS is hinting at a second quarter announcement of functi onal systems booting Unix, but less optimistic sources are not expecting systems using the CMOS chip to appear before the middle of next year.

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CBR Staff Writer

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