The emitter coupled logic – ECL – three chip VSLI set comprises the R6000 processor, clocked at 66.7MHz and expected to go to 80MHz and 65 MIPS by the middle of next year, the R6010 floating point controller chip, and R6020 system bus chip. Features include an on-chip memory management unit, two level cache, and separate instruction and data caches. It is supported by an input-output sub-system capable of providing 200Mbytes-per-second cumulative input-output bandwidth. On the RC6280 box, this is spread across multiple independent VME buses. As with the R2000 and R3000, initial versions of the R6000 are being manufactured for MIPS by Bipolar Integrated Technology, though Sony and NEC are due to start delivering the parts shortly.
