Sign up for our newsletter
Technology / AI and automation


Along with its multimedia extensions MIPS Technologies Inc has also introduced a 16-bit variant of its reduced instruction set for embedded applications. The MIPS16 set cuts the 106 instructions in the MIPS II set down to 38, a 40% reduction in code size over conventional MIPS embedded code, maintaining compatibility with standard MIPS 32-bit and 64-bit instruction sets. And system memory requirements are also cut by 40%. The company claims that MIPS processors can now compete with chips that, despite lower performance, were used in embedded applications because they offered smaller code sizes, such as the 40MHz Motorola 68ECO40 or the 25MHz Intel 486SXL. The variant was designed by MIPS in conjunction with one of its semiconductor partners, LSI Logic Corp, which introduced the first implementation, the TR4101TinyRISC, at the same time. Target applications for TinyRISC include cellular phones, video games, set-top boxes, digital scanners and smartcards -applications where system cost is a major consideration. The chip is implemented in 0.25 micron CMOS technology. LSI will accept designs using the TinyRISC core from December, when samples and evaluation boards will be ready. The design evaluation kit costs $4,000, while packaged TinyRISCs will cost around $10. The core should sell for around $25 when combined with other functions in a systems-on-a-chip design.

White papers from our partners

This article is from the CBROnline archive: some formatting and images may not be present.

CBR Staff Writer

CBR Online legacy content.