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LSI LOGIC’s 100,000 GATE ARRAY

LSI Logic Corp, Milpitas, California has perfected a proprietary 0.7-micron channel length HCMOS process, using it to create a semicustom gate array twice as dense as the most complex previously offered. Called the LCA100K Compacted Array Plus, it has 100,000 usable gates, equivalent to 400,000 transistors. It can incorporate a RISC microprocessor to control computers, engineering workstations and industrial controls and application-specific memory can be included in addition to logic. Gate delays are under 460pS, memory access times typically less than 15nS. A three-layer metal interconnect technology ena-bles more gates to be used and a more compact version of LSI’s Channel-Free architecture improves cus-tomisation. A 0.7 micron test chip is out and designs are under way.

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CBR Staff Writer

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