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July 22, 1990


By CBR Staff Writer

Sparc fabricator LSI Logic Corp, Milpitas, California is hedging its bets in the RISC wars and has come out with what it claims is the first off-the-shelf chip set for use in designing a complete computer system around the MIPS Computer Systems Inc R3000 RISC, which it also fabricates. The five-chip Mipset is claimed to replace 40 or more standard logic circuits and is pitched at Unix-based protable computers, X Window terminals, laser printers and other peripherals. The Mipset was developed in Japan by LSI Logic KK, and it is designed for use with LSI’s LR3000 CPU, which has on-chip memory management and cache control, and the LR3010 floating-point accelerator. The new set comes in 20MHz and 25MHz versions, comprises LR3201 reset/interrupt controller, LR3202 bus controller, LR3203 DRAM controller, LR3204 DRAM data controller and LR3205 block transfer buffer. The bus controller provides a direct interface with the LR3000 cache bus; separate DRAM, input-output and boot ROM interfaces; DRAM interface timer; and logic and stall-cycle generation to co-ordinate data transfer and memory access in multiprocessor applications. The LR3204 DRAM data buffer functions as an 8-bit device, so four are needed in the system. The LR3205 block transfer buffer has four independent direct memory access channels with an 8-word by 32-bit bidirectional First-In First-Out buffer, and byte or word assembly/disassembly for each channel. It can be cascaded to provide up to 64 channels of direct memory access. Optional interfaces are available for the Am7990 Lance or NCR 5390 SCSI bus interface chips. Samples of the set are available now, volume is set for the fourth quarter and the set, including LR3000 CPU and LR3010 maths chip to make 10 chips in total, is $704 at 20MHz, $1,097 for 25MHz when you order 1,000 or more of the sets.

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