Milpitas, California-based LSI Logic has a new Compacted Array Turbo series of gate arrays that, combined with LSI Logic’s libraries and design tools, is said to provide a complete package for system design: the LCA200K family is fabricated in 0.7 micron HCMOS technology which offers a combination of application-specific logic and high-density memory; the devices offer 20,000 to 200,000 usable gates with a customer-defined memory capability up to 36Kb of random access and 160Kb of read only memory; the libraries include Intel, AMD and Motorola industry-standard functions, as well as Sparc and MIPS microprocessors and peripherals; to support the new LCA200K series, LSI says it has developed a more accurate modelling technology that exploits the non-linear characteristics of sub-micron features; both two and three-layer interconnects are available, and two-layer metallisation is designed for low gate count designs with extensive input-output, while three-layer metal is said to enable high levels of functional integration; the line fully supports the IEEE Joint Test Action Group standard test scan techniques, and packaging options include ceramic or plastic pin grid arrays, ceramic or plastic leaded chip carriers, plastic quad flat pack, or chip on tape; prototypes of the LCA200K Compacted Array Turbo series will begin shipping this month with production shipments in June; engineering costs start at $75,000.
