LSI Logic Corp, headquartered in Milpitas, California has announced its second generation Embedded Array: the LEA200K Embedded Array Series, a new family of submicron 215,250 gate ASIC devices, is said to combine the performance and memory integration of cell-based designs with the prototype turnaround times of the Compacted Array offering; with up to 307,500 available gates and 215,250 usable random gates, the LEA200K family is claimed to offer 60% greater integration and up to 30% better performance than its predecessor; the product enables the integration of compiled embedded memory of 256K-bits static RAM with 64,000 customer defined logic gates; with 13 masterslice sizes, ranging from 66,156 to 307,500 available gates, the memory compiler enables the embedding of high-density, cell-based memory functions anywhere within the core; both two and three-layer metal interconnect schemes are available, the former for limited input output designs, the latter for implementing high-density designs of up to 215,250 gates; LEA200K devices use the enhanced modelling scheme in LSI Logic’s Concurrent Modular Design Environment design tools, which exploits the non-linear characteristics of submicron device features to increase simulation accuracy; packaging options include ceramic or plastic pin-grid array, ceramic or plastic leaded chip carrier, plastic and metal quad flat pack, and chip on tape; prototypes began shipping last month, with production shipments in September.
