Lattice Semiconductor and Praesum Communications have launched Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family. The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds.
Lattice said that the combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will allow customers to develop low-power infrastructure services for 3G, LTE and WiMAX. The Serial RapidIO 2.1 core and other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise an IP suite in support of wireless infrastructure applications.
According to Lattice, the Serial RapidIO 2.1 IP core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces. The core architecture for the Serial RapidIO 2.1 IP core features include, providing infrastructure support for external logical layer functions; provides a choice of logical layer functions that are important for the application; and a choice of how logic layer functions interact with the rest of the system.
In addition, its features implementation of physical layer, transport layer, maintenance transaction handling and error management extensions; supports software implementations of control plane oriented functions such as doorbells and messages; and backward compatible with the v1.3 specification.
Kent Dahlgren, CEO of Praesum, said: As the only supplier of fully compliant RapidIO 2.1 IP, Praesum’s partnership with Lattice will help to accelerate deployment of this next generation technology in high performance signal processing applications. When combined with our RapidIO 2.1 switching IP, the endpoint IP for the LatticeECP3 FPGA represents a complete solution for wireless infrastructure equipment vendors.
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