According to Moore’s Law, the transistor count on a chip roughly doubles every 18 months and the MIPS count doubles every 14 months, and, according to Intel Corp, the P6 successor to the Pentium will maintain this, with 300 MIPS and 6m transistors. Initially, the company will produce a 133MHz P6 with an integrated 256Kb second level cache, following up with a 512Kb cache. Intel is also expected to unveil a P6SX chip, without the integrated second-level cache unit. But Intel is aiming the new chip squarely at the server market, with a large built-in 512Kb secondary cache to improve transaction processing performance, and an improved version of Intel’s on-board Advanced Processing Interrupt Controller for handling multi-processing chores and improvements on such tasks as cache coherency, vital for robust multiprocessing, and data reliability, analogous to the parity checking in memory chips. The integration of the large second level cache into the chip package will be one of the major departures of the P6 from past processors, since the personal computer vendor traditionally designs its own second level cache, and this could create ructions if vendors feel unable to differentiate their products. The secondary cache and the P6 will communicate via a closely-linked, high-speed bus. The on-chip cache will also be boosted to 32Kb in the P6 from the Pentium’s 16Kb in the P6. The processor will have an improved superscalar design that can issue more instructions per clock cycle and better handle out-of-order instructions. The differences of Pentium’s successor come from the progress made in semiconductor packaging technology for cache memory, enhanced multiprocessing logic, four integer execution units and data reliability. A high performance Peripheral Component Interconnect chip set based on the P6 will also be available. The P6, fully software compatible with the 80386 and 80486, will rate over 200 in the SPECint92 ratings and is expected to ship in the second half of 1995.
