Intel Corp has a humdinger on its hands with the N-10 RISC microprocessor – a 1m transistor part in 1 micron CHMOS that includes 32-bit integer unit, paging unit and bus unit, 64-bit floating point unit with add, multiply and three-dimensional graphics unit, each taking up a third of the chip, the balance being given over to 4Kb instruction and 8Kb data caches, all built around a 64-bit bus. The part, clocked at 50MHz, is rated at 50 MIPS integer, 100MFLOPS and 150m operations per second peak since up to three indtructions can execute concurrently. More soberly, it does 105,000 Dhrystones and 21 MFLOPS on the double precision Linpack inner loop. Intel says that although the part, work on which began in 1986, can be used with an 80386 or upcoming 80486 front-ending it, it was always designed as a stand-alone CPU. It will support Unix, and can also be used to emulate other architectures, so that it could be used as the basis of machines to run IBM’s MVS or DEC’s VMS. It is also easy to emulate the Motorola 68000 on it, rather harder to do the 80386! Intel sees it as perhaps being the saviour of some minicomputer companies with proprietary architectures, since it should enable an order of magnitude reduction in price – $10,000 to $25,000 compared with over $100,000 for the current graphics supercomputer; in that mode, it is claimed to be able to do 60,000 shaded polygons a second against 20,000 for a Sun-4. Internal sampling has been going on since September, and direct memory access, input-output and disk controller support chips are fully developed – but Intel concedes that it does still have bugs in it. A sampling schedule is expected on February 27. The N-10 will be pitched partcularly at engineering and graphics workstations and multiprocessing computers, which suggests that the 80960 being used by Intel’s BiiN Inc joint venture with Siemens AG may be a stop-gap to the N-10.
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