Intergraph Corp is set to come out with the latest iteration of its Clipper chip set with the C400, which will be introduced at the Microprocessor Forum in California on October 10. The upward compatible 50MHz CMOS chip set aims at single-cycle integer execution, but like IBM’s RS/6000 RISC chip it claims to be superscalar by having the ability to perform floating point and integer operations in the same clock cycle. Like its predecessors, the chip is also superpipelined, increasing the pipeline stages to allow a higher clock rate: initial versions will be at 40MHz, but the 50MHz version at 1 micron will be scaled up to 70MHz using 0.5 micron CMOS technology. Intergraph is very shy about issuing a notoriously inaccurate blanket MIPS rating for the chip, but provides performance data from small segments of the Systems Performance Evaluation Council benchmarks – achieving 50 MIPS using the Espresso integer benchmark, 56 MIPS using the Spice scalar benchmark and up to 94 MIPS and 33.3 MFLOPS using the vector Linpack Daxpy inner loop benchmark. Samples fourth quarter, systems (from Intergraph) early next year. Its major customer for Clipper, Du Pont Co, is now considering using the new version.
