The EPIC parallel processing techniques Intel Corp and Hewlett- Packard Co have created for their IA-64 64-bit architecture are informed by VLIW very long instruction word techniques pioneered by the likes of Multiflow Computers Inc – many of whose engineers ended up at the two companies – but overcome two of VLIW’s crippling dependencies; scaling and compatibility. Jerry Huck, manager and lead architect at HP and John Crawford, Intel’s director of microprocessor architecture say EPIC relieves the requirement to hardwire the width of instructions and memory latency into VLIW designs. For Merced, HP, Intel and third party compilers will take original source code, expose instructions which can be performed as discrete or predicated operations and turn that into parallel machine code the CPU is specifically built to process. It uses large register files – up to 128-bits to provide headroom – and contains many replicated function units so that instructions predicated by the compiler can processed using larger and more economical basic blocks, eliminating the need for conventional branch prediction techniques used by conventional architectures that waste valuable resources when they fail. It uses speculation to limit unnecessary loading operations. Existing code will have to be recompiled – not re- written – to take advantage of EPIC techniques, though the companies stress that it will run existing binaries unchanged. The two companies say they’ll unveil more details of IA-64 techniques as Merced approaches. They say other companies my choose to implement EPIC techniques, although their IA-64 implementation of the concepts are patented. HP says it will provide system-level electronics and software that will enable PA-RISC instructions to execute on IA-64.
