The people heading up Intel’s Enterprise Platforms Group briefed reporters and analysts yesterday, but didn’t divulge all the details will undoubtedly be spilled at IDF next month.
Much of the information that Intel gave out this week is a more precise version of information that the company first divulged at the fall Developer Forum in September. With Intel making only a few server-related processor announcements a year, it tends to go over the same ground a few times, raising the curtain a little higher each time until announcement day. This is ever the way in the IT racket.
In any event, Intel’s briefings yesterday were, as usual, a cheerleading session for the 64-bit Itanium. Tom Garrison, who is marketing director for the Enterprise Platforms Group in Europe, said that Intel is working on six future generations of Itanium processors, which includes the dual-core Montecito due in 2005 and the multiple core Tukwila due after that in 2006 or so.
Tukwila is being co-designed with the engineers who used to work on the Alpha processor at Digital and Compaq before Compaq dumped the line and sold the chip and its people to Intel. It was briefly known by the code-name of Tanglewood, just so you don’t get confused. The Shavano or Chivano dual-core Itanium that was originally due in 2006 was killed off in favor of making Montecito a dual-core chip. What the code names are for the other four future Itanium chips, no one yet knows.
Going forward, Intel plans to roll out a Madison Itanium 2 processor running at more than 1.5GHz clock speed and having 9MB of L3 cache memory. The current top-end Madison runs at 1.5GHz and has 6MB of L3 cache, and it seems likely that a 1.8GHz or maybe even a 2GHz Madison could be delivered as Intel ramps up its 130 nanometer processes.
This article is based on material originally published by ComputerWire
