At a briefing ahead of the International Solid States Circuit Conference in San Francisco this week, Nimish Modi, general manager of the vendor’s Enterprise Processor Division, outlined an Itanium roadmap which features ever larger level three cache in successive chip generations.

The next generation of Itanium 2, Madison, is due for release this summer. This will be built on 0.13 micron technology, will feature upto 6MB of on-die level three cache, and will run at 1.5GHz. Summer 2004 will see the release of Madison 9M. This will also be built on 0.13 micron technology, but will feature upto 9MB of cache, and will have a top speed of more than 1.5GHz.

Modi highlighted the boosting of cache as a distinguishing feature of the Itanium family. Montecito, due in 2005, will feature at least 18MB of on die cache, split between the two cores. The two cores will be managed by an arbiter which will present the die as a single chip to the outside world.

Modi also emphasized Intel’s efforts to ensure drop-in compatibility between the current McKinley socket architecture and Madison and Montecito. This would be assured at least until Montecito. At the same time he acknowledged Intel was examining other bus architectures.

Even if Intel did pull the plug on the McKinley bus after Montecito, this would still mean OEMs would have received four years on a consistent architecture, he said. With Intel looking to refresh its Itanium line on an annual basis, said Modi, socket compatibility was one of the reasons OEMs can absorb new Itaniums.

Modi also said the company planned to bring its hyperthreading technology to Itanium. Hyperthreading effectively makes a single processor look like a dual processor system to software.

Modi did not say whether this would happen before Montecito is launched, and would not comment on the implications of having a dual core system containing two cores which themselves appear like dual cores to software. However, he did say that a dual core system still gets more performance than hyperthreading.

Unsurprisingly Intel is also examining multi core Itanium systems. The right number of cores is something we’re evaluating, said Modi. The trade off came in terms of power, he said. Every core you add, you’ve got to look at power.

While the vendor is trumpeting the high levels of cache Madison and Madison 9M will have, it will also offer versions with less cache, and potentially lower frequencies. That way it can offer three differentiated products targeted at high, middle and low-range applications.

Source: Computerwire