Intel also announced that the Paxville MP variant would be ready early.
According to an Intel spokesperson, the reason why the Paxville Xeon DP processor is being announced even though the company is working on the Dempsey 64-bit, dual-core processor for the Bensley platform for deliveries late in 2005 or early 2006 is that the development cycle and the yield on the silicon process used in the future Paxville Xeon MP chip for servers with more than four processors is so good that Intel was compelled to kick out a variant of this chip that would run in existing platforms.
A cynic might say that Intel is doing this as a stop-gap maneuver to blunt the advantages that rival Advanced Micro Devices has right now in the dual-core processor space for two-socket and four-socket servers, but things are rarely that simple. If Intel can create a Paxville DP processor – which was not originally on its roadmap – then it would be downright foolish to wait until early 2006 to peddle Bensley systems, which will arguably have better features in terms of the gadgets that the chipsets will support.
So in this regard, making some kind of 64-bit, dual-core, Xeon DP chip was a bit of a necessity, since this is the belly of the server market. And with server makers Dell Inc, Fujitsu-Siemens, and NEC Corp still not peddling Opteron-based servers while rivals Hewlett-Packard Co and Sun Microsystems Inc enthusiastically pushing Opteron alternatives and even IBM Corp offering one rack server and one blade server with the dual-core Opterons, Intel clearly had to do something. Six months is a long, long time in the server racket, and Intel has to meet AMD head-on and that means giving Dell, Fujitsu-Siemens, NEC, and others who are selling Intel-based gear something to counter with.
The new Paxville DP (short for dual processor, but maybe we should start calling these things DS for dual socket) is the third dual-core chip that Intel has added to its roadmap to flesh it out since it went whole hog for dual-core chips at the Intel Developer Forum in the spring.
The Paxville MP chip is part of the Truland server platform, which was launched earlier this year for the Cranford small cache and Potomac large cache Xeon MP platform. The Cranford and Potomac chips, which were due at the end of 2004, are Intel’s first generation of 64-bit processors in the Xeon line; they only have one core per chip.
The Truland platform also has PCI Express I/O, DDR2-400 main memory, Execute Disable (XD) security, error correction on the system bus, memory, RAID, and PCI Express buses, Demand-Based Switching (DBS) power management features, and a 667 MHz double-pumped front side bus.
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At the spring IDF, Intel said it would roll out a kicker to the Truland platform that will include the Tulsa large cache and Paxville small cache 64-bit Xeon MPs, which have two cores per chip. At that time, Intel said it expected to have these dual-core Xeon MPs will be available in the first quarter of 2006.
The Paxville chip is a single-die chip with two 1 MB caches (one per core), and it has two Xeon MP cores on a single piece of silicon, side by side sharing a split front side bus; some Intel chips have two chips sharing a single socket, but the chips are two separate processors that are glued together in multichip module (MCM) packaging. The Paxville MP chip uses a 90 nanometer process, while the larger-cache Tulsa chip will be made in a 65 nanometer process; it is unclear if Tulsa uses MCM techniques or will be a true dual-core chip.
With today’s announcement, Intel is moving up the Paxville MP processor, which uses its existing E8500 chipset, to sometime later in 2005 – exactly when, Intel is not yet saying, but Intel is saying the 90 nanometer yields are good enough and the demand for dual-core, 64-bit server chips is high enough that it can get these platforms out the door this year rather than waiting until early next year.
Even if the machines are not available until late October or early November, this change in the server roadmap has the desired effect: causing customers who might have been contemplating a move to a four-socket, dual-core Opteron machine to pause and rethink their options. Intel is not saying exactly when the Paxville MPs will be available in the Truland platform, which is now called the 7000 Series, but it is saying that the new servers will offer about 60 percent more performance than the single-core Cranford platforms. Cranford is no slouch, either.
It is hard to say if the advent of the Paxville DP version of this chip means that the Dempsey chip and its related Bensley platform is slipping. Intel surely is not copping to this if it is indeed the case. But clearly, Intel needed to do something in the two-socket server space to blunt AMD’s advantages, and creating a DP variant of the Paxville chip that plugs into the existing Lindenhurst platforms is a lot better than waiting for a whole new Bensley platform and watching AMD make some money and perhaps grow its market share in the next two to three quarters.
That said, Intel is being very careful to pitch the Paxville DP and Lindenhurst combo as an early adopter option for those who want dual core chips in two socket servers, not the mainstream, high-end Bensley box with the future Dempsey chip, which will also be a dual-core, 64-bit Xeon DP; however, Dempsey is really two Nocona Xeon DP cores, each with a 1 MB cache, implemented in a 65 nanometer process that are packaged in a single MCM that plugs into a single Xeon socket.
The Bensley platform will use a chipset codenamed Blackford, which will come in a flavor for regular two-socket servers as well as a version called Blackford-VS for so-called value servers. The Bensley platform includes support for fully buffered DIMM memory – which increases memory bandwidth and overall system performance, particularly for multicore designs – as well as a new I/O feature called I/O Acceleration Technology (I/OAT), which speeds up the performance of TCP/IP and other CPU-related messaging technologies by making tweaks in the CPU, in the chipset, in software compilers, and in operating systems. The Dempsey Xeon DP, which will also be available in a workstation platform called Glidewell, will presumably run a lot cooler than the Paxville Xeon DP as well.
The Paxville Xeon DP chip will only be available running at a 2.8 GHz clock speed. With a 2 MB cache and an 800 MHz front side bus, it will offer about a 50 percent performance increase compared to existing Lindenhurst machines, which are based on the Irwindale Xeon DPs, which 64-bit processing and memory addressing, but which have only a single core per socket.
The Paxville Xeon DP and Paxville Xeon MP processors have HyperThreading as well as multiple cores, which means they have two physical threads per socket, each with two virtual threads for a total of four virtual threads per socket. Pricing on the Paxville chips will be announced when they become available, as will wattage figures. It is hard to guess where either will end up.
Intel says that it will be getting thousands of dual-core platforms based on these Paxville processors, as well as on the future Montecito dual-core Itaniums and the Pentium D entry server chips, into the hands of software developers starting today. Exactly how software vendors will get these is a bit unclear, but they will probably get them directly through Intel in some cases as freebies or low-cost development boxes or through Intel’s OEM server partners on a similar basis.
With software development and certification programs taking anywhere from six to nine months, Intel has to get as many boxes in the hands of ISVs right now if it wants to create a wave of adoption among customers in early 2006 for dual-core, 64-bit server platforms. Intel is shipping its development platforms to ISVs with the kitchen sink: its C++ and Fortran compilers, threading tools, performance analyzers, and performance libraries.
