Mike Fister, general manager of Intel’s Enterprise Platforms Group, said just enough about its Xeon and Itanium processor plans for the next two years to make its systems partners hungry without telling them everything on the menu.

Taking it from the bottom up, Fister said that the Nocona Xeon DP processors that Intel would deliver in the second quarter would run at 3.6GHz and would have 1MB of L3 cache memory.

Up until now, Intel had not divulged the feeds and speeds of Nocona, other than to say that the chips would support 400MHz DDR2 ECC main memory and an 800MHz front side bus.

The Nocona will support the Lindenhurst chipset for dual-processor servers and the Tumwater variant aimed at high-end workstations; motherboards based on these chipsets will be able to support up to 16GB of main memory in four slots using 4GB DIMMs that uses considerably less power and generates a lot less heat than machines using 1GB or 2 GB DDR DIMMs

The future Jayhawk kickers to Nocona will also work in the Lindenhurst and Tumwater chipsets, and are probably Nocona’s with larger cache and more features activated that are latent in their cores (like HyperThreading was latent in the prior Northwood Pentium 4s and 64-bit was latent in the new Prescott Pentium 4s). Further out in 2005, Intel will deliver new chipsets that support the Jayhawks as well as an as-yet unnamed successor to them in the Xeon DP line.

In the second half of 2005, Intel will roll out a dual-core implementation of Potomac called Tulsa. It is not yet clear if the Tulsa processor will support HyperThreading as well as chip multithreading.

Fister said that all of the Xeons going forward would support three different modes: 32-bit applications on 32-bit operating systems, a so-called legacy mode; 32-bit applications running in compatibility mode on a 64-bit capable operating system; and a full-blown 64-bit mode for applications running on a 64-bit operating system.

On the Itanium MP front, Fister said that the updated Madison Itanium 2 processor that is expected in the second half of this year would include 9 MB of L3 cache and would run at 1.7GHz. It will probably provide about 15% more performance on workloads that don’t care all that much about L3 cache than the current 1.5GHz Madison chip, but could do a bit better than that on cache sensitive applications.

The news at this IDF was centered more on the Itanium DP front. The current Deerfield Low Voltage Itanium 2 DP processors, which ship in two-way servers aimed primarily at HPC clusters, current run at 1GHz or 1.4GHz and have 1.5MB of L3 cache. Later this year, Intel will launch a new Itanium DP chip dubbed Fanwood that will come in the regular DP and the low-voltage DP flavors. The Fanwood DP will run at 1.6Ghz and have 3MB of L3 cache, while the LV Fanwood DP will slow down slightly to 1.2GHz and have 3MB of L3 cache.

This article is based on material originally published by ComputerWire