The Prescott chip is pin-compatible with the Northwood, which means that the uniprocessor servers that are being sold in droves by Dell Inc, IBM Corp, Fujitsu Siemens, and Hewlett Packard Co can get a decent cache memory upgrade and support for HyperThreading.
HT is Intel’s version of simultaneous multithreading, which presents two virtual cores to an operating system even though there is only one core. Such multithreading can boost the performance of machines by 20% to 30%.
Intel says that when you test common desktop workloads using Northwood and Prescott cores running at the same clock speed, you get about the same performance – the HT benefits are cancelled out by the longer pipeline.
Even if HT does not immediately provide a performance boost in terms of raw performance, servers that are running multiple jobs simultaneously certainly benefit from it. For instance, a firewall running on a server will have less of an impact on the performance of other applications. And the larger L2 cache memory in the chips is also a good thing for entry servers.
The Prescott chip has 16 KB of L1 cache and 1MB of L2 cache, and Intel executives are trying to give the impression that the move from 55 million to 125 million transistors is die to this doubling of cache.
They must assume that no one looks very carefully at the pictures. Intel has a habit of putting features – such as HT – into chips and then only activating them after its manufacturing processes ramp up or the situation suits it. HT was lurking in the Northwood P4 and the Foster Pentium 4 Xeon MP for servers, for instance, and was only activated in a later stepping of the chips. People are suspicious that Prescott has electronics to support 64-bit extensions, and it just might turn out to be right.
If you look at the Prescott die picture that Intel gave to journalists, the picture is about 8.5 centimeters on a side, or 72.25 square centimeters. The increased L1 and L2 caches are clearly labeled and represent 16 square centimeters of space on the picture.
In a Northwood chip at 90 nanometers (if the thing existed), the caches would presumably only be 8 square centimeters, if the picture were taken at the same scale. But Northwood used a larger 130 nanometer process, so its caches would be a lot bigger physically – about by a factor of two.
Assuming a reasonable distribution of transistors over these areas, Prescott has about 1.7 million transistors per centimeter in the picture. So doubling the L1 and L2 caches should have only added about 13.6 million transistors to the Prescott compared to the Northwood. The die doesn’t lie, and there’s not more than meets the eye with Prescott.
No matter what, the Prescotts are good news for many entry server makers and buyers, since existing P4 machines can already support Prescotts and make good use of HT, larger caches, and 800MHz front side bus.
This article is based on material originally published by ComputerWire
