Tim Prickett-Morgan contributed to this story
IBM Corp’s next generation Power4 PowerPC RISC processor is to be previewed at the Hot Chips Conference at Stanford University later this month. Power4 is expected to be used in RS/6000s and AS/400s in the 2001 and 2002 timeframe. In a session entitled A 1GHz Power4 Testchip Design processor design leaders Brad McCredie and Roger Bailey will introduce the chip, which has been up and running as a test version since mid-December last year.
The Power4 test chip, which has 35 million transistors, has most of the basic design elements of the full Power4 chip, but is not the complete chip. Implemented in IBM’s 0.18 micron CMOS-7S copper and silicon-on-insulator chip technologies, it includes seven layers of metal and operates at 1GHz, five times the clock speed of the current Power3 processors on the market. It will include many of the advanced chip and caching technologies that IBM has been testing out in prior generations of 32-bit 604e and 64-bit Northstar/Pulsar PowerPC processors. The Power4 will have bigger L1 caches, and will also borrow IBM’s smart caching L2 cache technology, which first made its debut in the RS/6000 F50 and H50 PowerPC 604e servers.
Power4 will also incorporate two whole processors on a single piece of silicon, essential creating an on-chip SMP cluster. These individual microprocessors will include two floating point units, plus three integer units and an assortment of load and branch units. In other words, they will look very much like the current Power3 processors, except that they will include all of the AS/400 instructions included in the Northstar/Pulsar chips.
Running at 1.1GHz, the chip is likely to provide 8.8 peak theoretical gigaflops of number crunching power thanks to the four total math units, and will likely be able to process ten integer instructions per cycle, yielding a whopping 11,000 MIPS of raw power: that’s in the neighborhood of a 130 to 140 SPECint95 rating, ten times that of the current 200MHz Power3 processor. The follow-on Power4-II chip, due in 2002 or 2003, will use improved 0.13 micron copper and SOI processors, and will have clock speeds in the range of 1.5GHz. IBM does not have plans to add more Power chip modules to the Power4 complex, but says that it is investigating increasing the on-chip SMP from two-way to possibly four-way, eight-way or even more individual processors. The Power4s will be used in all RS/6000 workstations and servers and AS/400e servers. IBM does not know where Power4 will appear first, and all the company has said for sure is that in the 2001 to 2002 timeframe, it will have Power4 machines with 32-way SMP, 512Gb of main memory and up to 6Tb of disk attached to a single server. It is likely that initial Power4 boxes will have 16-way external traditional SMP capability as well as support for ccNUMA clustering, yielding an effective 32-way server.
IBM will hope the new chip will draw some of the attention from Intel Corp’s IA-64 processor, which will other wise be the focus of the Hot Chips conference. Intel plans to hold a detailed tutorial on the IA64 Architecture and compilers on the first day of the event, Sunday August 15th, in advance of its own Developers Forum in Palm Springs at the end of the month. The Power4 presentation takes place on Monday 16th. IBM plans to reveal further details of the Power4 at the Microprocessor Forum, which is to be held in San Jose and begins on October 4th. On Tuesday at Hot Chips, Sun Microsystems Inc’s Marc Tremblay will offer a session on Sun’s newly announced MAJC Microprocessor Architecture for Java Computing (CI No 3,716).
