IBM’s prototype 128K-bit fast 0.5 micron channel, 1 micron lithography CMOS static memory chip (CI No 1,118), has an access time of 6.5nS, but the pipelining feature that enables data to be written and read concurrently brings the effective rate down to 5nS – and it took seven people – Fred Towler, Jeff Chu, Russell Houghton and Paul Lane of the General Technology Division at Essex Junction, Vermont, B A and T I Chappell and S E Schuster of the Thomas J Watson Research Center in Yorktown Heights, New York to write the paper chip given at last week’s International Solid State Circuits Conference in New York.
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