IBM Corp is ready with a new generation of its Rios RISC, the RIOS 2 for June or July launch, which will be able to execute as many as six instructions per clock cycle, the same source reports. It doubles up branch and conditional registers and integer and floating point units and a version of the PowerPC, derived from the design, is expected to execute up to four instructions per cycle, although whether those kinds of superscalar performances can often be achieved in practice will depend on how well the compilers are optimised for the new internal architecture. The trade weekly hears that one version of Rios 2 combines nine separate chips on a substrate 4 square.
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