The joint IBM Corp-Motorola Inc-Apple Computer Inc Somerset development lab now says that the PowerPC process design schedule we’ve been shown does not define a specific set of process targets, but should be regarded as a general statement of design direction. The 106 PCI bridge memory controller family will never be done in 0.15 micron technology, for example. Meanwhile the symmetric multiprocessing-enabled Red October version of PowerPC 620 that Motorola Inc begins shipping to partners next month, is being fabricated in its 0.35 micron PTC 2.0 process. Red October is not expected to find its way into systems until the end of this year or the beginning of next. A 166MHz version of the 604e due in the summer is done in the same fabrication process. Somerset claims it is working on another PowerPC road map that neither Motorola nor IBM is willing to make public. Neither has made public its intent or otherwise, to make 620s.
