IBM Corp has finally introduced its single-chip implementation of the Power instruction RISC architecture as the 135MHz and 120MHz Power2 Super Chip. The 135MHz part is rated at 6.17 SPECint95 and 17.6 SPECfp95, the 120MHz version does 5.61 SPECint 95 and 16.6 SPECfp95. The 135MHz Power2 is deployed in a new RS/6000 Model 595 technical server which comes in above the 77MHz Power2-based Model 591. The Micro Channel bus machine has eight slots, 2Gb to 75Gb disk, and 64Mb to 2Gb memory. IBM is offering its threaded version of the Phigs graphics library with the systems – a threaded version of OpenGL is promised by mid-1997. It costs from $47,500. It has also implemented the 135MHz unit as a Wide Node for its SP parallel systems costing from $48,000 – a 120MHz Thin Node will cost from $58,000. The Wide Node includes an embedded SCSI-2 Fast/Wide interface, freeing up a Micro Channel slot previously required for a SCSI adapter, four Micro Channel slots, 64Mb to 2Gb memory and up to 18Gb disk and supports 16-way and eight-way High Performance Switch (old switch) or SP (new) switches. The 120MHz P2SC Thin Node comes with up to 1Gb memory, 9Gb disk and supports both switches. Existing 66MHz and 77MHz P2 Wide Nodes can upgrade to the 135MHz Wide Node and the Thin Node-2 to the 120MHz Thin Node. The SP nodes and the 595 run AIX 4. 2. The new PCI servers will get AIX 4. 2, now six months old, by the middle of 1997.
