During a keynote speech at the conference of IBM partners, Zeitler wandered off his prepared remarks and proclaimed that IBM’s future Power5 based servers, due in early 2004, would have quadruple the performance of the current pSeries 690 line. According to IBM sources, HP’s top brass has been saying that IBM was not a technology company any more, and Zeitler wanted to demonstrate that this was not the case as he talked to the Blue faithful.
That quadrupling of power is in rough agreement with what we’ve been hearing from parties in the know about Power5, which by the way used to be code-named Armada but which is now called Squadron inside Big Blue’s development and marketing organizations because another vendor is using the Armada code-name, too. (We hear it is HP, but have been unable to confirm.) By saying it, Zeitler is committing IBM to reach this performance goal in the next nine to 12 months, when the Power5 servers will launch. This is not normal IBM behavior, but then again, we do not live in normal times. It is tough out there, and every vendor is looking for any advantage they can get. That’s why HP is talking about its future Pinnacles 64-way chipset for PA-RISC and Itanium 2 processors, even though the machines won’t be ready for months. IBM is talking about Power5 machines because it knows that if HP can get 64-way Itanium 2 and 128-way PA-RISC machines in the field in the second half of this year, these machines will tromp IBM’s then-current Power4-based machines on most benchmark tests. Zeitler wants to remind everyone before that even happens that the company is preparing to leapfrog HP soon after it leapfrogs IBM in the Unix racket, probably some time in the second quarter of 2004.
In early January, we told you that the scuttlebutt was that IBM would be trying to hit 2 million transactions per minute with the initial Power5 Squadron servers. What appears to be more accurate is that IBM’s initial tests on Power5 machines in the lab show that on some workloads – which are not TPC-C or any derivative of it – the top-end 64-way Squadron machines are showing the potential for quadruple performance over the 32-way Power4 Regatta-H servers. It’s very likely that IBM is using a mix of Java and HPC benchmarks to characterize the performance increase, since these workloads are denser and more CPU and cache intensive than the TPC-C test. So a top-end 64-way Squadron server using 2GHz or faster Power5 dual-core processors might have four times the oomph of a 32-way pSeries 690 server using dual core 1.3GHz Power4 processors on some workloads, the improvement on the TPC-C test is uncertain. It might be 1.5 million transactions per minute (TPM), 2 million TPM, or 2.5 million TPM, depending on how all the new gadgets and circuits in the Squadron boxes pan out. The pSeries 690 hit 427,760 TPM.
In any event, the Power5 processor was sparked up in the IBM labs three weeks ago, according to IBM sources, running a set of assembly language test code, and before March is done, Power5 will boot up native AIX and Linux operating systems. It is very likely that OS/400, the iSeries midrange server operating system, will be booted up on the chip in IBM’s Rochester, Minnesota labs about the same time.
The Power5 processors will be implemented in the same 0.13 micron process used to create the 1.2 GHz and 1.45 GHz Power4+ processors used in the four-way pSeries 630 machines announced today and the pSeries 650 machines announced in November 2002. We have heard that they will run at 1.5GHz to 2GHz. The Power5+ processors, due sometime in 2005, will use a 0.09 micron chip-making processes and could scale from 2GHz to 3GHz or faster. The Power5 and Power5+ chips are dual-core processors with a shared L2 cache memory and external L3 caches integrated on multichip modules. The Power4 MCMs had 1.44 MB of L2 cache, and the Power4+ chips have 1.5 MB of L2 cache on each dual-core chip. With the Power5 chips, IBM will jack up the size of the L2 cache to around 1.9 MB to 2 MB. The main memory controller and L3 cache controllers will also be put inside the chip, which will reduce latencies and speed up throughput. The Power5 chips would support simultaneous multithreading, a technology that allows a single multipipelined processor to present two virtual images of itself to an operating system, and 64-way symmetric multiprocessing. We have also heard that IBM is planning to put some extra database and networking acceleration chips into the Power5 multichip modules to speed up common commercial workloads. It will almost certainly use some derivative of the PowerPC design for this work, perhaps an embedded PowerPC chip or maybe one of the future PowerPC 970 chips it is making for Apple Computer for its desktops and servers. Everything that an auxiliary processor in the MCM can do to speed up database work leaves more work for the main processors in the Armada complex to do.
Source: Computerwire
