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October 15, 1998

IBM ADDS NEW 405 POWERPC CORE, CODE COMPRESSION

By CBR Staff Writer

Intent on pushing the PowerPC processor into the embedded systems marketplace, IBM Corp has added a new PowerPC core to its Blue Logic embedded core library, along with new code compression technology. The PowerPC 405 core builds on the existing 401 core by using .25 micron process technology (compared with .35 micron for the 401) and a 200MHz clock speed (compared with the 401’s 80MHz). The 405 also has an extended, five-stage pipeline and other architectural improvements. IBM claims a three times performance increase over the existing 401 cores. The code compression technology is said to reduce code size by 40%. Using algorithms developed by IBM’s Research Labs, 32-bit instructions are converted to variable length instructions. The decompression is carried out by a 1mm square piece of hardware logic, also part of the Blue Logic library, and applicable to any of the PowerPC cores. IBM says the approach is more efficient than techniques used by ARM Ltd for the Thumb processor, and MIPS Technologies Inc, both of which convert 32-bit instructions to 16-bit extensions, reducing the power of the instructions. The 401 has already been used for system-on-a-chip designs used in shipping products, says IBM. Laser printer controllers in products from Ricoh Corp, Canon Inc and Minolta Corp use the core as part of a complete controller supplied by Peerless Systems Corp. Spokesman Dean Parker said that IBM was working towards making the embedded PowerPC an open architecture, similar to the ARM chip.

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