Hewlett-Packard Co is having trouble getting its microprocessor story straight, which is perhaps not surprising given the disclosure restrictions placed upon it by its partner Intel Corp. However, HP wants to make it clear that it will continue to develop its PA-RISC architecture in parallel with systems based upon Intel’s forthcoming Merced chip for a period (CI No 3,206). HP executives were last week drawing us diagrams of how Merced and PA-RISC development streams meet around the year 2000, maybe Q2 1999. They told us we’ll support existing [PA- RISC] customers and help them transition over [to Merced], but we do want them to transition over. We will not have a two-chip strategy. HP has already identified at least one further PA-RISC iteration which will follow the mid-1998 PA-8500 (CI No 3,181). HP would not comment on when future PA-RISC chips or Merced systems would be introduced. It claims a performance lead for its current 200MHz PA-8200 which executes floating-point instructions at 23 SPECfp95 according to an industry benchmark, compared with DEC’s 600MHz Alpha 21164, which performs at 21.3 SPECfp95.
