HP announced yesterday new research that uses nanoelectronic architecture that essentially allows microprocessors to tolerate defaults, which spells lower chip-making costs.

By using what’s known as cross-bar architecture and nanowires, the researchers promise to do away with the need of perfect chips, which today require $3bn factories to manufacture.

If successful, HP’s technology may obsolete the chip industry’s current curve of making chips with smaller features at a higher cost. (Today, 90-nanometer chip geometries are common and 65-nm chips already are being piloted.)

Part of the beauty of the new technology, which HP said is at least 10 years away from commercialization, is that it may both integrate with and potentially replace future versions of existing CMOS (complementary metal-oxide semiconductor) technology.

It’s a friendly way to implement disruptive technology, said David Lackner, a senior analyst at Lux Research.

HP Labs researcher Stan Williams said future chips will have to rely, at least in part, on the crossbar architecture.

Rather than use transistors, crossbar circuits use a set of parallel nanowires that are laid on another set of parallel wires at a right angle, which sandwiches a layer of electrically switchable material in between. Where the material becomes trapped between the crossing wires, they form a switch that represents a 1 or 0, the basic building blocks of computer code.

Even if there is a partial disconnect between the crossbar and the rest of the circuitry, the nanowires will continue to function. Lackner said it was analogous to the ESP technology used, way back when, to prevent portable CP players from skipping when jarred.

It’s like giving a distinctive name to a restaurant host to be sure you hear your party called above the noise of the crowd, said Phil Kuekes, a senior HP computer architect. Instead of ‘the Jones party,’ you might put yourself down as ‘the John Paul Jones party.’ That way, when the host calls your name, you’ll hear it, even if every word doesn’t come through clearly.

HP said the result could be nearly perfect manufacturing yield with equipment a thousand times less expensive than what might be required using future versions of current technologies.

HP’s architectural approach for future microprocessor differs radically from Intel’s focus in this area. Intel has 100 or so ongoing research projects and may already be researching crossbar architecture, but it mainly has been involved, at least publicly, in developing new types of microprocessor materials.

Most of what I’ve seen in nanoelecronics has been new materials and new forms of manufacturing, so this is interesting in that this is a new way of architecting, said Lawrence Gasman, principal analyst at NanoMarkets. Presumably it could be implemented in different forms of materials.

While it is far too early to tell just how microprocessors will look in 10 or 15 years’ time, one potential advantage to HP’s research is it is built upon proven fundamental approaches, Gasman said.

After all, crossbar is nothing new – crossbar switches have been used in telephone networks for many years, albeit in a completely different context and size. HP’s research also relies on coding theory, a 60-year-old theory used in mathematics and telecommunications today. While HP is using these methods in a new way, at least there is some form of knowledge base available.

Inventing something that’s utterly new can be seriously cool, but … it takes forever to develop, Gasman said.