Hewlett-Packard Co’s Merced systems are expected to be multiprocessor affairs using the crossbar switch technology from its Convex Computer Corp acquisition. Merced chips will be packaged in groups of four or six in a similar manner to the forthcoming Pentium Pro Standard High Volume boards. A system will be composed of Hypernodes, groups of eight Merceds sharing local memory with four-port isochronous crossbar switches providing point-to-point links inside the node. Each port has 250Mbps band width with the switch total being 1Gb per second. Hypernodes will be connected by a Scalable Coherent Interconnect forming what Hewlett-Packard calls a two-dimensional toroidal mesh with global shared memory. Because of the delays associated with accesses between hypernodes, a ccNUMA – cache-coherent non-uniform memory architecture – will be needed and will be a feature of the combined HP-UX-OpenServer-UnixWare Merced operating system being produced with Santa Cruz Operation Inc’s help. Input- output channels and devices connect to memory with a second set of crossbar switches. Disk storage subsystems network connections and input-output buses will hook up to a switch port. The first systems from Hewlett-Packard using Merced Hypernodes wi ll appear in early 1998 and are provisionally called SPP3000s for scalable parallel processing, the next generation of Convex’s SPP series. Unlike Tandem, which is licensing its ServerNet Asynchronous Transfer Mode-like bus-replacement technology to third parties, Hewlett-Packard is keeping its crossbar switch in-house. We are told that compilers for the systems will feature a Convex front-end and Hewlett-Packard back-end.
