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April 1, 1987


By CBR Staff Writer

The first generation 32-bit microprocessor optimised for Japan’s Tron – The Real-time Operating Nucleus – won’t be ready until the end of the year, but already the two partners on the chip, Fujitsu and Hitachi, are looking ahead to a second generation version of the part that is being designed to run at 20 MIPS. The first generation, dubbed either the H or the F32/200, depending on whether you get it from Hitachi or Fujitsu, is set for sampling at the end of the year, and has been designed to deliver 10 MIPS, topping the 7 MIPS rating put on the forthcoming Motorola 68030 that Toshiba will be manufacturing in Japan. The part will be offered to support Cobol under Unix System V as an alternative to ITron, which is the version of Tron that has been tailored for industrial applications. The second generation 32/300 will have an enhanced pipeline architecture, on-board virtual memory manager and a gigantic 4Kb on-chip cache, and will be fabricated in CMOS to one micron design rules.

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