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November 15, 1993

HEWLETT-PACKARD PLANS TO TAKE ADDRESSING OF ITS PRECISION ARCHITECTURE RISC TO 96 BITS

By CBR Staff Writer

Spurred on by Digital Equipment Corp’s boasts of 64-bit processing with the Alpha, Hewlett-Packard Co has begun dropping hints about the next generation of RISC technology in its research labs in Palo Alto, California and Bristol, UK. According to Wim Roelandts, Hewlett-Packard vice-president and general manager, Computer Systems, DEC’s flat addressing implementation of 64-bit technology is fine for scientific processing but less suitable for transaction processing. Hewlett-Packard already uses 64-bit addressing split into two parts on the current Precision Architecture RISC, which is a distinct advantage for transaction processing work, says Roelandts. The next generation will keep this segmentation, while expanding the chip to 96 bits. Roelandts says there that will be no need for users to re-engineer their software to move to it. DEC, he says, currently has the best CMOS process technology in the business, but Roelandts reckons that it has concentrated on high clock speeds at the expense of everything else. He promises higher clock speeds from Hewlett-Packard within the next 12 months, saying that the company currently achieves similar performance at 110MHz to 120MHz as DEC does at 200MHz.

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