Rather than see the Precision Architecture RISC squeezed out in the battle for RISC design wins, Hewlett-Packard Co has decided to throw in its lot with the winner by a distance of the microprocessor race and merge its future 64-bit RISC architecture with that of Intel Corp – if the US regulatory authorities give it the nod. The two yesterday announced that they are joining forces on a research and development project to develop the chips that will be needed for workstations, servers and enterprise computing products by the end of the decade. The implication is that it is likely that the P7, the first member of the iAPX-86 family planned to be primarily a RISC, will derive those RISC techniques from Precision Architecture. The companies confirmed that the work that Hewlett-Packard is doing on Very Long Instruction Word Trace compilers (CI No 2,326, 2,322) will be a key part of the joint development effort. The companies said only their efforts will encompass 64-bit microprocessor designs, advanced semiconductor processes and software optimisation. They said that by pooling their strengths, they expect to create powerful products that will maintain binary compatibility with both companies’ software bases. This effort with Intel is aimed at providing a unified computing infrastructure that accomplishes three fundamental goals: preserves current customer investments, readies corporate customers for the next century, and offers high-volume cost models, Richard Sevcik, general manager of Hewlett-Packard Systems & Server Group, said.
