GigaLogician, a new high-performance hardware accelerator for the mixed-level simulation of large electronic system designs, has been introduced by Daisy Systems Corp, Mountain View, which says it is capable of simulating designs of 96,000 to 256,000 primitives. The company claims, however, that the GigaLogician architecture is designed to accommodate designs of 1m to 3m primitives. The GigaLogician uses a multiprocessor parallel architecture that uses two distinct types of processors for simulation. Hard-wired processors accelerate switch- and gate level simulation tasks. Microcoded processors accelerate both behavioural simulation tasks and input from Daisy’s physical modeller, PMX, which fits directly into the GigaLogician chassis. The base configuration of the GigaLogician comes with one hard wired processor and two microcoded processors. Each hard-wired processor can simulate 64,000 switch- and gate-level primitives at up to 1.75m evaluations per second. Each microcoded processor can simulate 16,000 behavioural and physical modeller primitives at 100,000 evaluations per second. A network resource in Daisy’s computer-aided engineering environment, GigaLogician is from $180,000, $45,000 for each additional hard-wired processor, $20,000 for each additional microcoded one. It will be available in August.
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