The ICS-8551 offers both two- and four-channel operation with sampling frequencies of 1.5 GHz (four channel) or 3 GHz (two channel) for Software Defined Radio (SDR) applications such as spectrum monitoring, signal intelligence, tactical communications and radar.
The ICS-8551 HDK includes both a default logic core and a Digital Down-Converter (DDC) IP core. The default logic core, designed to provide minimum occupancy of the FPGA, provides a basis for customers to program their own functionality. It includes an A/D interface and data buffering to the high-speed serial outputs and to the PCI bus, via FIFO buffers. The DDC core enables a band-limited signal at a given (programmable) Intermediate frequency to be shifted in frequency to base band, then filtered and decimated prior to output. Output options include the high-speed serial outputs or the PCI bus. Other features including protocol cores will be added to the HDK in future.
