A consortium comprising ES2, Matra MHS, Mietec, and STC, along with Plessey Research, CNET (France), and IMEC (Belgium), have won a contract under the European Community’s Esprit research support programme. They submitted a proposal last year for the initiative to create a common European process technology for silicon chips below the 1.0 micron level, and signed the contract at the beginning of May. The project is designed to develop a European capability in ASIC CMOS chips in attempt to reduce dependency on US and Japanese manufacturers. The team aims to develop, demonstrate, and qualify a 0.7 micron process by the end of 1991, and demonstrate a 0.5 micron process during 1992. Applications are to be designed by British Telecom, Acatel SEL and Telefonica – the three associate partners in the project. These partners can also offer the same design rules to customers in a further attempt to reduce dependency and develop multi-sourcing.
