Things could be ugly in the brave new world of EPIC explicitly parallel instruction level computing for some time to come – bad news for those counting on Intel Corp’s first generation Merced chip for any real work. Wen-mei Hwu, professor of electrical and computer engineering at the University of Illinois, and chief technology officer of the Impact compiler group, warns that, although compilers are critical to the performance of EPIC CPUs, the use of prediction and speculation required by the architecture is still a serious challenge. Any misuse by programmers will lead to a loss of performance, not just break even. Not only that, EPIC compilers need brand new algorithms, most of which are still being developed in the labs, and are not yet stable enough for commercial deployment. He says performance robustness issues are only to be expected, with some applications showing awesome performance leaps while others will see much less due to the limitations of analysis and optimizations. It will take years before the performance gains are universal. Hwu also told attendees at the Microprocessor Forum that, just as in the early days of RISC, architectures are likely to undergo extensive revisions as the compiler technologies mature. And before EPIC architectures can be used effectively for embedded applications, issues of code size and power consumption will need to be addressed.
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