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December 17, 2018updated 18 Jul 2022 7:50am

DARPA Delegates Look to POSH Chips, Page 3 for Defence Inspiration

"DARPA envisions the tech world moving toward a wider variety of SoCs with different mixes of IP blocks, including highly customized SoCs for specific applications"

By CBR Staff Writer

In two days’ time, delegates will walk into a Hilton hotel in Arlington, Virginia with a clear purpose: support a US semiconductor manufacturing base that is capable of implementing highly specialised circuits that “can be trusted through the supply chain” – and work out how new chips and advanced electronics can be put to defence use.

The so-called “proposer’s day” is part of a $1.5 billion project, the Electronics Resurgence Initiative (ERI), launched last year and run by the Defense Advanced Research Projects Agency (DARPA); the branch of the Pentagon responsible for the development of emerging technologies.

Its aim: breathing fresh life into Moore’s Law as semiconductor innovation slows, the use of custom programmable hardware like FGPAs grows and fears of Chinese IP theft and hardware dominance proliferate.

Advanced Electronics for “Large-Scale Emulation”

At the meeting this Wednesday, DARPA participants will discuss innovations emerging under a previous funding round of its Electronics Resurgence Initiative and propose [pdf] the application of these advanced electronics to future defence.

The purposes to which innovations can be directed: “Autonomy/artificial intelligence, large-scale emulation, cybersecurity, space applications, cognitive electronic warfare, and intelligence, surveillance and reconnaissance (ISR)”.

Attendees will also “have a chance to provide input on how best to support the transition of electronics innovations into national defense hardware.”

“Novel Circuit Materials, Architectures, and Designs”

“The first phase of ERI was a major investment into the R&D required to stay competitive by exploring specialization with novel circuit materials, architectures, and designs,” said Dr Bill Chappell, director of DARPA’s Microsystems Technology Office, announcing Phase II of the ERI programme early last month.

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He added: “ERI Phase II seeks to build on that investment and push us toward a domestic semiconductor manufacturing sector that can implement specialized circuits; demonstrate that those circuits can be trusted through the supply chain and are built with security in mind; and are ultimately available to both DoD and commercial sector.”

“DARPA seeks to procure the expertise and transition support of industry and the defense community to help accelerate the delivery of ERI-derived innovations for national security needs,” he added in a later note ahead of the proposers’ day.

Electronics Resurgence Initiative: A Boost in a Tech Arms Race

The meeting comes amid a growing technological arms race with China and concerns about hardware security exacerbated by a widely criticised – some would say discredited –  Bloomberg article that alleged Chinese tampering with hardware used in servers run by 30 major US companies, including Apple and Amazon.

See also: China Put Spy Chips in Servers Used by Apple, Amazon, Major Banks: Bloomberg

While the Bloomberg piece has convinced few information security professionals, concerns about both Chinese IP theft and hardware tampering abound.

In a Washington Post editorial late Friday, for example, Michael Morell, twice acting director of the CIA and David Kris, a former assistant attorney general for national security, argued that an ongoing trade war with China is, in fact, a “tech war”.

As they noted: “Just last month, the statutorily created U.S.-China Economic and Security Review Commission reported [pdf] to Congress that the Chinese government may ‘force Chinese suppliers or manufacturers to modify products to perform below expectations or fail, facilitate state or corporate espionage, or otherwise compromise the confidentiality, integrity, or availability of [Internet of Things] devices or 5G network equipment. That is a sobering consideration, especially when public-private partnerships in the United States are in a period of relative ebb.”

They added: “There may not be an end to this technological cold war anytime soon, but it is vital for our national security that we not cede the field.”

Read this: Post-Super Micro Controversy: How Secure Is My Hardware?

Intel staff test new chips... Electronics Resurgence Initiative: DARPA Chip Project to Boost Security

Intel staff test new chips

DARPA’s leaders meanwhile note that as Moore’s Law (crudely, processing power doubles every year) stumbles, System-on-a-Chip (SoC) designers are spending less on CPUs and more on GPUs, FGPAs and neural chips.

As contributor Eric Brown puts it: “Such divergent applications often require highly divergent mixes of processors, including novel chips like neural net accelerators. DARPA envisions the tech world moving toward a wider variety of SoCs with different mixes of IP blocks, including highly customized SoCs for specific applications. With today’s semiconductor design tools, however, such a scenario would bog down in spiraling costs and delays. ERI plans to speed things up.”

Moore’s Law: Page 3

DARPA’s inspiration lies on page three of a 1965 paper.

Moore’s Law, defined on pages one and two of Gordon Moore’s seminal 1965 paper entitled “Cramming More Components onto Integrated Circuits,” has guided the electronics industry for more than 50 years.

As technological and economic barriers emerge to its continuance, page three of Moore’s paper described research areas required to manage this possibility.

“In deference to Moore’s ideas” DARPA has organised ERI investments are organized into the areas he described – Architectures, Designs, and Materials and Integration.

  • The Architectures Thrust asks whether the electronics community can enjoy the benefits of specialised circuitry while still relying on general programming constructs through proper software/hardware co-design
  • The Designs Thrust asks whether the electronics community can dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialisation and innovation
  • The Materials and Integration Thrust asks whether the integration of unconventional materials can enhance conventional silicon circuits and continue the progress traditionally associated with scaling…

With these three areas in mind (and funded) DARPA wants to see an eclectic alphabet soup of emerging chip types emerge under the Electronics Resurgence Initiative.

Electronics Resurgence Initiative

Not that kind of posh chip…

These include: “Common Heterogeneous Integration and Intellectual Property Reuse Strategies (CHIPS), Three Dimensional Monolithic System-on-a-Chip (3DSoC), Foundations Required for Novel Compute [pdf] (FRANC), Software Defined Hardware (SDH), Domain-specific System on Chip (DSSoC), Intelligent Design of Electronic Assets (IDEA), Posh Open Source Hardware (POSH)” and more.

See this: Intel Unveils New Architectures: Open API, 3D Stacking, More

Eric Brown sums them up tidily in his July blog covering the first funding round.

IDEA — Is based primarily on work by David White at Cadence, which received $24.1 million of IDEA funding. The immediate goal is to create a layout generator that would enable users with even limited electronic design expertise to complete the physical design of electronic hardware such as a single board computer within 24 hours.

Software Defined Hardware (SDH) — SDH aims to develop hardware and software that can be reconfigured in real time based on the kind of data being processed. The goal is to design chips that can reconfigure their workload in a matter of milliseconds. Stephen Keckler at Nvidia is leading the funding at $22.7 million.

Domain-Specific System on Chip (DSSoC) — The DSSoC project is inspired by software defined radio (SDR). The project is working with the GNU Radio Foundation to look at the needs of SDR developers as the starting point for developing an ideal SDR SoC.

3DSoC — This semiconductor materials and integration project is based largely on MIT research from Max Shulaker, who received $61 million. FRANC is attempting to grow multiple layers of interconnected circuitry atop a CMOS base to prove that a monolithic 3D system using a more affordable 90nm process can compete with CPUs

Foundations Required for Novel Compute (FRANC) — FRANC is looking to improve the performance of NVM memories such as embedded MRAM with a goal of enabling “emerging memory-centric computing architectures to overcome the memory bottleneck presented in current von Neumann computing.”

Such emerging electronic technologies, DARPA notes, would help address not just national security objectives, but offer “strategic surprise”. Wednesday’s meeting will give some ideas quite how surprising that surprise might be.

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